TMS320C80GF datasheet(38/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PP functional block diagram

Figure 22 shows a block diagram of a parallel processor. Key features of the PP include:

D 64-bit instruction word (supports multiple parallel operations)

D Three-stage pipeline for fast instruction cycle

D Numerous registers

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8 data, 10 address, 6 index registers

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20 other user-visible registers

D Data Unit

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16x16 integer multiplier (optional dual 8x8)

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Splittable 3-input ALU

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32-bit barrel rotator

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Mask generator

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Multiple-status flag expander for translations to/from 1 bit-per-pixel space.

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Conditional assignment of data unit results

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Conditional source selection

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Special processing hardware

Leftmost one / rightmost one

Leftmost bit change / rightmost bit change

D Memory addressing

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Two address units (global & local) provide up to two 32-bit accesses in parallel with data unit operation.

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12 addressing modes (immediate and indexed)

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Byte, halfword, and word addressability

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Scaled indexed addressing

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Conditional assignment for loads

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Conditional source selection for stores

D Program flow

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Three hardware loop controllers

Zero overhead looping / branching

Nested loops

Multiple loop endpoints

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Instruction cache management

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PC mapped to register file

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Interrupts for messages and context switching

D Algebraic assembly language

TMS320C80GF Datasheet(PDF) 38 Page - Texas Instruments

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