TMS320C80GF datasheet(20/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

master processor (MP) architecture

The master processor (MP) is a 32-bit RISC processor with an integral IEEE-754 floating-point unit. The MP

is designed for effective execution of C code and is capable of performing at well over 130K dhrystones/s. Major

tasks which the MP typically performs are:

D Task control and user interface

D Information processing and analysis

D IEEE-754 floating point (including graphics transforms)

MP functional block diagram

Figure 3 shows a block diagram of the master processor. Key features of the MP include:

D 32-bit RISC processor

–

Load/store architecture

–

Three operand arithmetic and logical instructions

D 4K-byte instruction cache and 4K-byte data cache

–

Four-way set associative

–

LRU replacement

–

Data writeback

D 2K-byte non-cached parameter RAM

D Thirty-one 32-bit general-purpose registers

D Register and accumulator scoreboard

D 15-bit or 32-bit immediate constants

D 32-bit byte addressing

D Scalable timer

D Leftmost-one and rightmost-one logic

D IEEE-754 floating-point hardware

–

Four double-precision floating-point vector accumulators

–

Vector floating-point instructions

Floating-point operation and parallel load or store

Multiply and accumulate

D High performance

–

60 million instructions per second (MIPS)

–

120 million floating-point operations per second (MFLOPS)

–

Over 130K dhrystones/s

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