TMS320C80GF datasheet(42/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

index registers

The six 32-bit index registers contain index values for use with the address registers in address computations

or they can be used for general-purpose data. Registers x0 – x2 are used by the local-address unit and registers

x8 – x10 are used by the global-address unit.

stack pointer (sp)

The sp contains the address of the bottom of the PP’s system stack. The stack pointer is addressed as a6 by

the local-address unit and as a14 by the global-address unit. Figure 27 shows the sp register format.

Word-Aligned Address

Figure 27. sp Register Format

zero register

The zero registers are read-as-zero address registers for the local address unit (a7) and global-address unit

(a15). Writes to the registers are ignored and can be specified when operational results are to be discarded.

Figure 28 shows the zero register format.

Figure 28. zero Registers

PP program flow control (PFC) unit registers

loop registers

The loop registers control three levels of zero-overhead loops. The 32-bit loop start registers (ls0 – ls2) and

loop-end registers (le0 – le2) contain the starting and ending addresses for the loops. The loop-counter registers

(lc0 – lc2) contain the number of repetitions remaining in their associated loops. The lr0 – lr2 registers are loop

reload registers used to support nested loops. The format for the loop-control (lctl) register is shown in Figure 29.

There are also six special write-only mappings of the loop-reload registers. The lrs0 – lrs2 codes are used for

fast initialization of ls

n, lrn, and lcn registers for multi-instruction loops while the lrse0 – lrse2 codes are used

for single instruction-loop fast initialization.

–

LCD2

LCD1

LCD0

LCDn

Loop End Enable

Loop Counter Designator

000 – None

010 – lc1

001 – lc0

011 – lc2

1xx – reserved

le2

le1

le0

Figure 29. lctl Register

pipeline registers

The PFC unit contains a pointer to each stage of the PP pipeline. The pc contains the program counter which

points to the instruction being fetched. The ipa points to the instruction in the address stage of the pipeline and

the ipe points to the instruction in the execute stage of the pipeline. The instruction pointer

return-from-subroutine (iprs) register contains the return address for a subroutine call. Figure 30 shows the

variable pipeline register format.

TMS320C80GF Datasheet(PDF) 42 Page - Texas Instruments

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