TMS320C80GF datasheet(72/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

packet-transfer parameters (continued)

Next Entry Address

PT Options

Src Start Address

Dst Start Address

Src B Count

Dst B Count

Src A Count

Dst A Count

Src C Count

Dst C Count

Src B Pitch

Dst B Pitch

Src C Pitch

Dst C Pitch

Transparency/Color Word 0

Transparency/Color Word 1

Don’t Care

Long-Form Parameter Table

PT+4

PT+8

PT+12

PT+16

PT+20

PT+24

PT+28

PT+32

PT+36

PT+40

PT+44

†PT+48

†PT+52

PT+56

PT+60

0†

1†

PT - 64-byte aligned on-chip starting address of

parameter table.

† These words are swapped in big-endian mode.

Byte

Address

Word

Number

Next Entry Address

PT Options

Src Start Address

Dst Start Address

Short-Form Parameter Table

PT+4

PT+8

PT+12

Byte

Address

Word

Number

Count

PT - 16-byte aligned on-chip starting address of

parameter table.

Figure 57. Packet-Transfer Parameter Table

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