TMS320C80GF datasheet(69/171 Pages) TI

69 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

TC architecture

The transfer controller (TC) is a combined memory controller and DMA (direct memory access) machine. It

handles the movement of data within the ’C80 system as requested by the master processor, parallel

processors, video controller, and external devices. The transfer controller performs the following data

movement and memory control functions:

D MP and PP instruction cache fills

D MP data cache fills and dirty block write-back

D MP and PP direct external accesses (DEAs)

D MP and PP packet transfers

D Externally initiated packet transfers (XPTs)

D VC packet transfers (VCPTs)

D VC shift register transfers (SRTs)

D DRAM/SDRAM refresh

D Host bus request

TC functional block diagram

Figure 52 shows a functional block diagram of the transfer controller. Key features of the TC include:

D Crossbar interface

–

64-bit data path

–

Single-cycle access

D External memory interface

–

4G-Byte address range

–

Dynamically configurable memory cycles

8-, 16-, 32-, or 64-bit bus size

Selectable memory page size

Selectable address multiplexing

Selectable cycle timing

–

Big- or little-endian operation

D Cache, VRAM, refresh controller

–

Programmable refresh rate

–

VRAM block write support

D Independent Src and Dst addressing

–

Autonomous addressing based on packet-transfer parameters

–

Data read and write at different rates

–

Numerous data merging and alignment functions performed during transfer

D Intelligent request prioritization

TMS320C80GF Datasheet(PDF) 69 Page - Texas Instruments

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