TMS320C80GF datasheet(86/171 Pages) TI

86 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

read cycles (continued)

col

ci‡

col

col†

col

State

CLKOUT

CT[2:0]

AS[2:0]

BS[1:0]

PS[3:0]

UTIME

FAULT

READY

RETRY

STATUS[5:0]

A[31:0]

RAS

CAS / DQM[7:0]

DSF

TRG / CAS

D[63:0]

DBEN

DDIN

UTIME

RAS

CAS / DQM[7:0]

Column C

Column B

Row

PAC

Cycle Type

Col A

Col B

Col C

For user-modified timing:

Column A

† Wait state inserted by external logic (example)

‡ Internally generated pipeline bubble (example)

Idle

PAC

0 For Normal Reads, 1 For PDPT Reads

Figure 67. 3 Cycles / Column Read-Cycle Timing

write cycles

Write cycles transfer data from the ’C80 to external memory. These cycles can occur as a result of a packet

transfer, a DEA request, or an MP data cache write-back. During the cycle TRG / CAS is held high, W is driven

low after the fall of RAS to enable early-write cycles, and DDIN is high so that data transceivers drive toward

memory. The TC drives data out on D[63:0] and indicates valid bytes by activating the appropriate CAS / DQM

strobes. During peripheral device packet transfers, DBEN remains high and D[63:0] is placed in high impedance

so that the peripheral device can drive data into the memory. Write cycles are shown in Figure 68 through

Figure 71.

TMS320C80GF Datasheet(PDF) 86 Page - Texas Instruments

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