TMS320C80GF datasheet(81/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

row states

The row states make up the row time of each memory access. They occur when each new page access begins.

The transition indicators determine the conditions that cause transitions to another state. See Table 35 and

Table 36.

Table 35. Row States

STATE

DESCRIPTION

Beginning state for all memory accesses. Outputs row address (A[31:0]) and cycle type (STATUS[5:0]) and drives control

signals to their inactive state

Common to all memory accesses. Asserts RL and drives DDIN according to the data transfer direction. AS[2:0], BS[1:0],

CT[2:0], PS[3:0] and UTIME inputs are sampled

Common to all memory accesses. DBEN is driven to its active level. For non-SDRAM, W, TRG / CAS, and DSF are driven to

their active levels and for non-SDRAM refreshes, all CAS / DQM strobes are activated. FAULT, READY, and RETRY inputs are

sampled.

Inserted for 3 cycle / column accesses (CT=111) only. No signal transitions occur. RETRY input is sampled.

Common to SDRAM and 2 or 3 cycle / column accesses (CT=0xx or 11x). RAS is driven low. W is driven low for DCAB and MRS

cycles and TRG / CAS is driven low for MRS and SDRAM refresh cycles.

Common to all memory accesses. For SDRAM cycles, RAS, TRG / CAS, and W are driven high. For non-SDRAM, RAS is driven

low (if not already) and W, TRG / CAS, and DSF are driven to their appropriate levels. DBEN is driven low and READY and

RETRY are sampled.

rspin

Additional state to allow TC column time pipeline to load. No signal transitions occur. RETRY is sampled. The rspin state can, on

occasion, repeat multiple times.

Common to 2 and 3 cycle / column refreshes (CT=11x). Processor activity code is output on STATUS[5:0]. RETRY input is

sampled.

For 3 cycle / column refreshes only (CT=111). No signal transitions occur. RETRY input is sampled.

Common to all refresh cycles. Processor activity code is output on STATUS[5:0] and RETRY input is sampled.

Occurs for pipelined 1 cycle / column writes only. All CAS / DQM strobes are activated.

dcab

Occurs for SDRAM cycles (CT = 0xx). RAS and W are activated to perform a DCAB command.

rhiz

High impedance state. Occurs during host requests and repeats until bus is released by the host

Table 36. State Transition Indicators

INDICATOR

DESCRIPTION

any cycle

Continuation of current cycle

CT=xxx

State change occurs for indicated CT[2:0] value (as latched in r2 state)

abort

Current cycle aborted by TC in favor of higher priority cycle

fault

FAULT input sampled low (in r3 state), memory access faulted

retry

RETRY input sampled low (in r3 state), row-time retry

wait

READY input sampled low (in r3, r6, or last column state) repeat current state

spin

Internally generated wait state to allow TC pipeline to load

new page

The next access requires a page change (new row access).

external memory timing examples

The following sections contain descriptions of the ’C80 memory cycles and illustrate the signal transitions for

those cycles. Memory cycles may be separated into two basic categories; DRAM-type cycles for use with

DRAM-like devices, SRAM, and peripherals, and SDRAM-type cycles for use with SDRAM-like devices.

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