TMS320C80GF datasheet(66/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

video controller architecture

The video controller (VC) provides a method for handling the video or graphics capture, or display portions of

a TMS320C80 system. It provides simultaneous control over two independent capture or display systems and

frame grabber or frame buffer image storage.

VC functional block diagram

Figure 46 shows a functional block diagram of the video controller. Key features of the VC include:

D Dual-frame timers

–

Independent or locked operation

–

Programmable horizontal and vertical timing

–

Separate or composite sync and blanking control

–

Synchronization to external timing signals

–

Interlaced or noninterlaced frame control

–

Virtually limitless screen resolutions

D Programmable timing and control registers

D Programmable line interrupt to MP

D Shift register transfer (SRT) controller

–

Generates VRAM serial register transfer requests to the TC

–

Tracks VRAM tap point and schedules midline reloads

–

Generates packet-transfer requests for DRAM-based buffer updates

–

Supports two display or capture buffers

On-Chip Register Bus (MP)

SCLK0

SCLK1

FCLK0

FCLK1

HSYNC0

VSYNC0

CSYNC0 / HBLNK0

CBLNK0 / VBLNK0

CAREA0

HSYNC1

VSYNC1

CSYNC1 / HBLNK1

CBLNK1 / VBLNK1

CAREA1

VC Request (to TC)

VC Register Interface

SRT Controller

FT0 Events

FT1 Events

Frame

Timer

Frame

Timer

Figure 46. VC Block Diagram

TMS320C80GF Datasheet(PDF) 66 Page - Texas Instruments

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