TMS320C80GF datasheet(4/171 Pages) TI

4 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

D Single-Chip Parallel Multiple

Instruction / Multiple Data (MIMD) DSP

D More Than Two Billion RISC-Equivalent

Operations per Second

D Master Processor (MP)

– 32-Bit Reduced Instruction Set

Computing (RISC) Processor

– IEEE-754 Floating-Point Capability

– 4K-Byte Instruction Cache

– 4K-Byte Data Cache

D Four Parallel Processors (PP)

– 32-Bit Advanced DSPs

– 64-Bit Opcode Provides Many Parallel

Operations per Cycle

– 2K-Byte Instruction Cache and 8K-Byte

Data RAM per PP

D Transfer Controller (TC)

– 64-Bit Data Transfers

– Up to 480M-Byte / s Transfer Rate

– 32-Bit Addressing

– Direct DRAM / VRAM Interface With

Dynamic Bus Sizing

– Intelligent Queuing and Cycle

Prioritization

D Video Controller (VC)

– Provides Video Timing and VRAM

Control

– Dual-Frame Timers for Two Simultaneous

Image-Capture and / or Display Systems

D Big- or Little-Endian Operation

D 50K-Byte On-Chip RAM

D 4G-Byte Address Space

D 16.6-ns Cycle Time

D 3.3-V Operation

D IEEE Standard 1149.1† Test Access Port

(JTAG)

GF PACKAGE

( BOTTOM VIEW )

GGP PACKAGE

( BOTTOM VIEW )

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

† IEEE Standard 1149.1–1990, IEEE Standard Test Access Port and Boundary-Scan Architecture

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