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TMS320C80GF Datasheet(PDF) 57 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 57 Page - Texas Instruments |
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57 / 171 page ![]() TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PP opcode formats (continued) Table 13. Parallel Transfer Mnemonics MNEMONIC FUNCTION 0bank Bits 5–3 of global transfer source/destination register code (bit 6 assumed to be 0) Adstbnk Bits 6–3 of ALU destination register code As1bank Bits 6–3 of ALU source 1 register code bank Bits 6–3 of global (or local) store source or load destination c Conditional choice of D register for src1 operand of the ALU C Protect status register’s carry bit cond Condition code d D register or lower 3 bits of register code for local transfer source/destination D Duplicate least significant data during moves dst The three lowest bits of the register code for move or field move destination dstbank Bits 6–3 of move destination register code e Sign extend local (bit 31), sign extend global (bit 9) g Conditional global transfer Ga Global address register for load, store, or address unit arithmetic Gim / X Global address unit immediate offset or index register Gmode Global unit addressing mode Grm Global PP-relative addressing mode itm Number of item selected for field extract move L L = 1 selects load operation, L = 0 selects store / address unit arithmetic operation La Local address register for load, store, or address unit arithmetic Lim / X Local address unit immediate offset or index register Lmode Local unit addressing mode Lrm Local PP-relative addressing mode N Protect status register’s negative bit r Conditional write of ALU result reg Register number used with bank or 0bank for global load, store, or address unit arithmetic s Enable index scaling. Additional index bit for byte accesses or arithmetic operations (bit 28, local; bit 6, global) size Size of data transfer (bits 30 – 29, local; bits 8 – 7, global) src Three lowest bits of register code for register-register move source or non-field moves. D register source for field move srcbank Bits 6–3 of register code for register-register move source V Protect status register’s overflow bit Z Protect status register’s zero bit – Unused bit (fill with 0) |
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