TMS320C80GF datasheet(78/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

page sizing (continued)

Table 33. Page-Size Selection

PS[3:0]

ADDRESS BITS COMPARED

PAGE SIZE (BYTES)

0 0 0 0

A(31:6)

0 0 0 1

A(31:7)

128

0 0 1 0

A(31:8)

256

0 0 1 1

A(31:9)

512

0 1 0 0

A(31:10)

0 1 0 1

A(31:18)

256K

0 1 1 0

A(31:19)

512K

0 1 1 1

A(31:20)

1 0 0 0

A(31:0)

1–8†

1 0 0 1

A(31:11)

1 0 1 0

A(31:12)

1 0 1 1

A(31:13)

1 1 0 0

A(31:14)

16K

1 1 0 1

A(31:15)

32K

1 1 1 0

A(31:16)

64K

1 1 1 1

A(31:17)

128K

† PS[3:0] = 1000 disables page-mode cycles so that the effective page size is the same

as the bus size

block write support

The TMS320C80 supports three modes of VRAM block write. The block-write mode is dynamically selectable

so that software may specify block writes without knowing what type of block write the addressed memory

supports. Block writes are supported only for 64-bit buses. During block-write and load-color-register cycles,

the BS[1:0] inputs determine which block mode will be used (see Table 34).

Table 34. Block-Write Selection

BS[1:0]

BLOCK-WRITE MODE

0 0

Simulated

0 1

Reserved

1 0

1 1

SDRAM support

The TMS320C80 provides direct support for synchronous DRAM (SDRAM), VRAM (SVRAM), and graphics

RAM (SGRAM). During ’C80 power-up refresh cycles, the external system must signal the presence of these

memories by inputting a CT2 value of 0. This causes the ’C80 to perform special deactivate (DCAB) and mode

by the ’C80. Note that read latency 4 timing programs the mode register for a read latency of 3. See Figure 60

for a listing of MRS values.

TMS320C80GF Datasheet(PDF) 78 Page - Texas Instruments

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