TMS320C80GF datasheet(36/171 Pages) TI

36 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

MP opcode summary (continued)

Table 7. Summary of MP Opcodes

INSTRUCTION

DESCRIPTION

INSTRUCTION

DESCRIPTION

add

Signed integer add

or.ff

Bitwise OR with 1s complement

and.tt

Bitwise AND

or.ft

Bitwise OR with 1s complement

and.ff

Bitwise AND with 1s complement

or.tf

Bitwise OR with 1s complement

and.ft

Bitwise AND with 1s complement

rdcr

Read control register

and.tf

Bitwise AND with 1s complement

rmo

Rightmost one

bbo

Branch bit one

shift.dz

Shift, disable mask, zero extend

bbz

Branch bit zero

shift.dm

Shift, disable mask, merge

bcnd

Branch conditional

shift.ds

Shift, disable mask, sign extend

Branch always

shift.ez

Shift, enable mask, zero extend

brcr

Branch control register

shift.em

Shift, enable mask, merge

bsr

Branch and save return

shift.es

Shift, enable mask, sign extend

cmnd

Send command

shift.iz

Shift, invert mask, zero extend

cmp

Integer compare

shift.im

Shift, invert mask, merge

dcache

Flush data cache sub-block

Store register into memory

estop

Emulation stop

sub

Signed integer subtract

fadd

Floating-point add

swcr

Swap control register

fcmp

Floating-point compare

trap

Trap

fdiv

Floating-point divide

vadd

Vector floating-point add

fmpy

Floating-point multiply

vmac

Vector floating-point multiply and add to ac-

cumulator

frndx

Floating-point convert/round

vmpy

Vector floating-point multiply

fsqrt

Floating-point square root

vmsc

Vector floating-point multiply and subtract

from accumulator

fsub

FLoating-point subtract

vmsub

Vector floating-point subtract accumulator

from source

illop

Illegal operation

vrnd(FP)

Vector round with floating-point input

jsr

Jump and save return

vrnd(Int)

Vector round with integer input

Load signed into register

vsub

Vector floating-point subtract

ld.u

Load unsigned into register

xnor

Bitwise exclusive NOR

lmo

Leftmost one

xor

Bitwise exclusive OR

or.tt

Bitwise OR

TMS320C80GF Datasheet(PDF) 36 Page - Texas Instruments

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