TMS320C80GF datasheet(28/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

MP cache registers

The ILRU and DLRU registers track least-recently-used (LRU) information for the sixteen instruction-cache and

sixteen data-cache blocks. The ITAGxx registers contain block addresses and the present flags for each

sub-block. DTAGxx registers are identical to ITAGxx registers but include dirty bits for each sub-block. Figure 17

shows the cache registers.

ILRU (0x0300)

DLRU (0x0500)

mru

nmru

nlru

lru

mru

nmru

nlru

lru

mru

nmru

nlru

lru

mru

nmru

nlru

lru

Set 3

Set 2

Set 1

Set 0

ITAG0 –ITAG15 (0x0200 – 0x020F)

22-Bit Cache Tag Address

Sub-Block

DTAG0 – DTAG15 (0x0400 – 0x040F)

22-Bit Cache Tag Address

Sub-Block

mru

nmru

nlru

Most-recently-used block

Next most-recently-used block

Next least-recently-used block

lru

Least-recently-used block

Sub-block present

Sub-block dirty

mru, nmru, nlru, and lru have the value 0, 1, 2, or 3 representing the block number and are mutually exclusive for each set.

Figure 17. Cache Registers

TMS320C80GF Datasheet(PDF) 28 Page - Texas Instruments

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