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TMS320C80GF Datasheet(PDF) 100 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 100 Page - Texas Instruments |
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100 / 171 page ![]() TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 97 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 block-write cycles (continued) c1 c2 c3 c1 c2 c3 c3 c1 c2 c3 col col r1 col C Col Sel C C CAS / DQM[7:0] RAS UTIME DDIN DBEN D[63:0] W TRG / CAS DSF CAS / DQM[7:0] RAS A[31:0] RL STATUS[5:0] RETRY READY FAULT UTIME PS[3:0] BS[1:0] AS[2:0] CT[2:0] CLKOUT State AB For user-modified timing: Col Sel B Col Sel A B A Col C Col B Col A Row PAC PAC PAC Cycle Type r1 r2 r3 r4 r5 r6 col col col col col col col† ci‡ Col A Col B Col C † Wait state inserted by external logic (example) ‡ Internally generated pipeline bubble (example) 7 Idle Figure 79. 3 Cycles / Column Block-Write-Cycle Timing |
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