TMS320C80GF datasheet(82/171 Pages) TI

82 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

DRAM-type cycles

The DRAM-type cycles are page-mode accesses consisting of a row access followed by one or more column

accesses. Column accesses may be one, two, or three clock cycles in length with two and three cycle accesses

allowing the insertion of wait states to accommodate slow devices. Idle cycles can occur after necessary column

accesses have completed or between column accesses due to “bubbles” in the TC data-flow pipeline. The

pipeline diagrams in Figure 63 show the pipeline stages for each access type and when the CAS / DQM signal

corresponding to the column access is activated.

CAS/DQM

Col A

-/A

A/B

B/C

C/-

Col B

Col C

Idle

Pipelined 1 cycle/column (CT = 100)

reads, read transfers, split read transfers

CAS/DQM

Col A

C-

Col B

Col C

Idle

Nonpipelined 1 cycle/column (CT = 101)

reads, read transfers, split read transfers

CAS/DQM

Col A

Col B

Col C

Idle

Nonpipelined 1 cycle/column (CT = 101)

writes, LCRs, block writes, write transfers, split write transfers

CAS/DQM

Col A

Col B

3 cycle/column (CT = 111)

all cycles (except refresh)

CAS/DQM

Col A

Col B

Col C

Idle

Pipelined 1 cycle/column (CT = 100)

writes, LCRs, block writes, write transfers, split write transfers

CAS/DQM

Col A c1

Col B

2 cycle/column (CT = 110)

all cycles (except refresh)

Col C

Idle

Col C

Idle

Figure 63. DRAM Cycle Column Pipelines

read cycles

Read cycles transfer data or instructions from external memory to the ’C80. The cycles can occur as a result

of a packet transfer, cache request, or DEA request. During the cycle, W is held high, TRG / CAS is driven low

after RAS to enable memory output drivers and DDIN is low so that data transceivers drive into the ’C80. The

TC places D[63:0] in high impedance allowing it to be driven by the memory and latches input data during the

appropriate column state. The TC always reads 64 bits and extracts and aligns the appropriate bytes. Invalid

bytes for bus sizes of less than 64 bits are discarded. During peripheral device packet transfers, DBEN remains

high. Read cycles are shown in Figure 64 through Figure 67.

TMS320C80GF Datasheet(PDF) 82 Page - Texas Instruments

TMS320C80GF Datasheet(HTML) 82 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL