TMS320C80GF datasheet(21/171 Pages) TI

21 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

MP functional block diagram (continued)

(Thirty-One 32-Bit Registers)

Scoreboard

Barrel Rotator

Double-Precision Floating-Point

Accumulators

Mask Generator

Zero Comparator

Integer ALU

Leftmost / Rightmost One

Timer

Double-Precision

Floating-Point Multiplier

(Single-Precision Core)

Control Registers

Instruction Register

Program Counters

PC Incrementer

Emulation Logic

Instruction Cache

Controller

Endian Multiplexers

Double-Precision

Floating-Point Adder

Data/Cache

Controller

Crossbar Interface

Figure 3. MP Block Diagram

MP general-purpose registers

The MP contains 31 32-bit general-purpose registers, R1 – R31. Register R0 always reads as zero and writes

to it are discarded. Double precision values are always stored in an even-odd register pair with the higher

numbered register always holding the sign bit and exponent. The R0/R1 pair is not available for this use. A

scoreboard keeps track of which registers are awaiting loads or the result of a previous instruction and stalls

the instruction pipeline until the register contains valid data. As a recommended software convention, typically

R1 is used as a stack pointer and R31 as a return-address link register.

Figure 4 shows the MP general-purpose registers.

TMS320C80GF Datasheet(PDF) 21 Page - Texas Instruments