TMS320C80GF datasheet(63/171 Pages) TI

63 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

addressing-mode codes

The Lmode (bits 35–38) and Gmode (bits 13–16) of the opcode specify the local and global transfer for various

parallel transfer opcode formats (Lmode in formats 1, 2, 3, 4, and 6 and Gmode in formats 1, 5, and 9). Table 22

shows the coding for the addressing-mode fields.

Table 22. Addressing-Mode Codes

CODING

EXPRESSION

DESCRIPTION

00xx

Nop (nonaddressing mode operation)

0100

*(an ++= xm)

Postaddition of index register, with modify

0101

*(an – – = xm)

Postsubtraction of index register, with modify

0110

*(an ++= imm)

Postaddition of immediate, with modify

0111

*(an – – = imm)

Postsubtraction of immediate, with modify

1000

*(an + xm)

Preaddition of index register

1001

*(an – xm)

Presubtraction of index register

1010

*(an + imm)

Preaddition of immediate

1011

*(an – imm)

Presubtraction of immediate

1100

*(an += xm)

Preaddition of index register, with modify

1101

*(an – = xm)

Presubtraction of index register, with modify

1110

*(an += imm)

Preaddition of immediate, with modify

1111

*(an – = imm)

Presubtraction of immediate, with modify

Legend:

Address register in l/g address unit

imm

Immediate offset

Index register in same unit as an register

L, e codes

The L and e bits combine to specify the type of parallel transfer performed, as shown in Table 23. For the local

transfer, L and e are bits 21 and 31, respectively. For the global transfer, L and e are bits 17 and 9, respectively.

Table 23. Parallel Transfer Type

PARALLEL TRANSFER

Zero-extend load

Sign-extend load

Store

Address unit arithmetic

size codes

The size code specifies the data transfer size. For field moves (parallel transfer format 3), only byte and halfword

data sizes are valid, as shown in Table 24.

Table 24. Transfer Data Size

CODING

DATA SIZE

Byte (8 bits)

Halfword (16 bits)

Word (32 bits)

Reserved

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