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TMS320C80GF Datasheet(PDF) 64 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 61 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 relative-addressing mode codes The Lrm and Grm opcode fields allow the local-address or global-address units, respectively, to select PP-relative addressing as shown in Table 25. Table 25. Relative-Addressing Mode Codes CODING RELATIVE-ADDRESSING MODE 00 Normal (absolute addressing) 01 Reserved 10 PP-relative dba 11 PP-relative pba Legend: dba – Data RAM 0 base is base address pba – Paramater RAM base is base address condition codes In the four conditional parallel transfer opcodes (formats 7–10), the condition code field specifies one of 16 condition codes to be applied to the data-unit operation source, data-unit result, or global transfer based on the setting of the c, r, and g bits, respectively. Table 26 shows the condition codes. For the 32-bit immediate data unit opcode (format D), the condition applies to the data-unit result only. Table 26. Condition Codes CONDITION BITS MNEMONIC DESCRIPTION STATUS BIT COMBINATION 35 34 33 32 0 0 0 0 u Unconditional (default) None 0 00 1 p Positive ~N & ~Z 0 01 0 ls Lower than or same ~C | Z 0 01 1 hi Higher than C & ~Z 0 10 0 lt Less than (N & ~V) | (~N & V) 0 10 1 le Less than or equal (N & ~V) | (~N & V) | Z 0 11 0 ge Greater than or equal (N & V) | (~N & ~V) 0 11 1 gt Greater than (N & V & ~Z) | (~N & ~V & ~Z) 1 0 0 0 hs, c Higher than or same, carry C 1 0 0 1 lo, nc Lower than, no carry ~C 1 0 1 0 eq, z Equal, zero Z 1 0 1 1 ne, nz Not equal, not zero ~Z 1 10 0 v Overflow V 1 10 1 nv No overflow ~V 1 11 0 n Negative N 1 1 1 1 nn Nonnegative ~N EALU operations Extended ALU (EALU) operations allow the execution of more advanced ALU functions than those specified in the base set ALU opcodes. The opcode for EALU instructions contains the operands for the operation while the d0 register extends the opcode by specifying the EALU operation to be performed. The format of d0 for EALU operations is shown in Figure 24. |
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