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TMS320C80GF Datasheet(PDF) 85 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 85 Page - Texas Instruments |
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85 / 171 page ![]() TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 82 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 read cycles (continued) r1 col col ci‡ col col† col col col r6 r5 r3 r2 r1 State CLKOUT CT[2:0] AS[2:0] BS[1:0] PS[3:0] UTIME FAULT READY RETRY STATUS[5:0] RL A[31:0] RAS CAS / DQM[7:0] DSF TRG / CAS W D[63:0] DBEN DDIN UTIME RAS CAS / DQM[7:0] C C C A B For user-modified timing: B A B A Col C Col B Col A Row PAC PAC Cycle Type c2 c1 Col A Col B c2 c1 Col C c1 c2 c2 0 For Normal Reads, 1 For PDPT Reads 6 † Wait state inserted by external logic (example) ‡ Internally generated pipeline bubble (example) Idle PAC Figure 66. 2 Cycles / Column Read-Cycle Timing |
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