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TMS320C80GF Datasheet(PDF) 24 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 21 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MP control registers In addition to the general-purpose registers, there are a number of control registers that are used to represent the state of the processor. Table 1 shows the control register numbers of the accessible registers. Table 1. Control Register Numbers NO. NAME DESCRIPTION NO. NAME DESCRIPTION 0x0000 EPC Exception Program Counter 0x0015–0x001F — Reserved 0x0001 EIP Exception Instruction Pointer 0x0020 SYSSTK System Stack Pointer 0x0002 CONFIG Configuration 0x0021 SYSTMP System Temporary Register 0x0003 — Reserved 0x0022–0x002F — Reserved 0x0004 INTPEN Interrupt Pending 0x0030 MPC Emulator Exception Program Cntr 0x0005 — Reserved 0x0031 MIP Emulator Exception Instruction Ptr 0x0006 IE Interrupt Enable 0x0032 — Reserved 0x0007 — Reserved 0x0033 ECOMCNTL Emulator Communication Control 0x0008 FPST Floating-Point Status 0x0034 ANASTAT Emulation Analysis Status Reg 0x0009 — Reserved 0x0035–0x0038 — Reserved 0x000A PPERROR PP Error Indicators 0x0039 BRK1 Emulation Breakpoint 1 Reg. 0x000B — Reserved 0x003A BRK2 Emulation Breakpoint 2 Reg. 0x000C — Reserved 0x003B–0x01FF — Reserved 0x000D PKTREQ Packet Request Register 0x0200 – 0x020F ITAG0 – 15 Instruction Cache Tags 0 to 15 0x000E TCOUNT Current Counter Value 0x0300 ILRU Instruction Cache LRU Register 0x000F TSCALE Counter Reload Value 0x0400–0x040F DTAG0 – 15 Data Cache Tags 0 to 15 0x0010 FLTOP Faulting Operation 0x0500 DLRU Data Cache LRU Register 0x0011 FLTADR Faulting Address 0x4000 IN0P Vector Load Pointer 0 0x0012 FLTTAG Faulting Tag 0x4001 IN1P Vector Load Pointer 1 0x0013 FLTDTL Faulting Data (low) 0x4002 OUTP Vector Store Pointer 0x0014 FLTDTH Faulting Date (high) MP pipeline registers The MP uses a three-stage fetch, execute, access (FEA) pipeline. The primary pipeline registers are manipulated implicitly by branch and trap instructions and are not accessible by the user. The exception and emulation pipeline registers are user accessible as control registers. All pipeline registers are 32 bits. Program Execution Mode Normal Exception Emulation Program Counter PC EPC MPC Instruction Pointer IP EIP MIP Instruction Register IR • Instruction register (IR) contains the instruction being executed. • Instruction pointer (IP) points to the instruction being executed. • Program counter (PC) points to the instruction being fetched. • Exception/emulator instruction pointer (EIP/MIP) points to the instruction that would have been executed had the exception / emulation trap not occurred. • Exception/emulator program counter (EPC/MPC) points to the instruction to be fetched on returning from the exception/emulation trap. Figure 9. MP FEA Pipeline Registers |
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