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TMS320C80GF Datasheet(PDF) 79 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 79 Page - Texas Instruments |
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79 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 76 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SDRAM support (continued) SDRAM Mode Register Bit 11 10 9 8 7 6 5 4 3 2 1 0 Meaning WB 0 0 Read Latency S/I Burst Length Value 0 0 0 0 0 !(UTIME) UTIME UTIME&CT0 0 0 0 CT1 UTIME, CT0, CT1 values as input at the start of the MRS cycle Figure 60. MRS Value Because the MRS register is programmed through the SDRAM address inputs, the alignment of the MRS data to the ’C80 logical-address bits is adjusted for the bus size (see Figure 61). The appearance of the MRS bits on the ’C80 physical-address bus is dependent on the address multiplexing as selected by the AS[2:0] inputs. ’C80 LOGICAL ADDRESS BITS BS[1:0] A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 X X X X 11 10 9 8 7 6 5 4 3 2 1 0 0 1 X X X 11 10 9 8 7 6 5 4 3 2 1 0 X 1 0 X X 11 10 9 8 7 6 5 4 3 2 1 0 X X 1 1 X 11 10 9 8 7 6 5 4 3 2 1 0 X X X Figure 61. MRS Value Alignment memory cycles TMS320C80 external memory cycles are generated by the TC’s external memory controller. The controller’s state machine generates a sequence of states which define the transition of the memory interface signals. The state sequence is dependent on the cycle timing selected for the memory access being performed as shown in Figure 62. Memory cycles consist of row states and the column pipeline (see Figure 62). |
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