TMS320C80GF datasheet(96/171 Pages) TI

96 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

block-write cycles

Block-write cycles cause the data stored in the VRAM color registers to be written to the memory locations

enabled by the appropriate data bits output on the D[63:0] bus. This allows up to a total of 64 bytes (depending

on the type of block write being used) to be written in a single-column access. This cycle is identical to a standard

write cycle with the following exceptions:

D DSF is active (high) at the fall of CAS, enabling the block-write function within the VRAMs.

D Only 64-bit bus sizes are supported during block write; therefore, BS[1:0] inputs are used to indicate the

type of block write that is supported by the addressed VRAMs, rather than the bus size.

D The two or three LSBs (depending on the type of block write) of the column address are ignored by the

VRAMs because these column locations are specified by the data inputs.

D The values output by the TC on D[63:0] represent the column locations to be written to, using the

color-register value. Depending on the type of block write supported by the VRAM, all of the data bits

are not necessarily used by the VRAMs.

D Block writes always begin with a row access. Upon completion of a block write, the memory interface

returns to state r1 to await the next access.

See Figure 76 through Figure 79 for block-write cycle timing.

TMS320C80GF Datasheet(PDF) 96 Page - Texas Instruments