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TMS320C80GF Datasheet(PDF) 97 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 97 Page - Texas Instruments |
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97 / 171 page ![]() TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 94 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 block-write cycles (continued) c1 c1 c1 PAC PAC CAS / DQM[7:0] RAS UTIME DDIN DBEN D[63:0] W TRG / CAS DSF CAS / DQM[7:0] RAS A[31:0] RL STATUS[5:0] RETRY READY FAULT UTIME PS[3:0] BS[1:0] AS[2:0] CT[2:0] CLKOUT State For user-modified timing: r1 r2 r3 r6 rspin rspin col col ci† col drn r1 C Sel C C AB Sel A B A Col C Col B Col A Row PAC Cycle Type Sel B Col A Col B Col C 4 † Internally generated pipline bubble (example) Idle Drain Figure 76. Pipelined 1 Cycle / Column Block-Write-Cycle Timing |
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