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TMS320C80GF Datasheet(PDF) 34 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 31 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 MP opcode summary (continued) Table 5. Long-Immediate and Three-Register Opcodes 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 trap – – – – E – – – – – 1 1 0 0 0 0 0 0 1 I – – – – – – – IND TR cmnd – – – – – – – – – – 1 1 0 0 0 0 0 1 0 I – – – – – – – Source1 rdcr Dest – – – – – 1 1 0 0 0 0 1 0 0 I – – – – – – – IND CR swcr Dest Source 1 10 0001 01 I – – – – – – – IND CR brcr – – – – – – – – – – 1 1 0 0 0 0 1 1 0 I – – – – – – – IND CR shift.dz Dest Source 1 1 0 0 0 1 0 0 0 0 i n Endmask Rotate shift.dm Dest Source 1 10 0010 010 i n Endmask Rotate shift.ds Dest Source 1 10 0010 100 i n Endmask Rotate shift.ez Dest Source 1 10 0010 110 i n Endmask Rotate shift.em Dest Source 1 10 0011 000 i n Endmask Rotate shift.es Dest Source 1 10 0011 010 i n Endmask Rotate shift.iz Dest Source 1 10 0011 100 i n Endmask Rotate shift.im Dest Source 1 10 0011 110 i n Endmask Rotate and.tt Dest Source2 1 1 0 0 1 0 0 0 1 I – – – – – – – Source1 and.tf Dest Source2 1 10 0100 10 I – – – – – – – Source1 and.ft Dest Source2 1 10 0101 00 I – – – – – – – Source1 xor Dest Source2 1 10 0101 10 I – – – – – – – Source1 or.tt Dest Source2 1 10 0101 11 I – – – – – – – Source1 and.ff Dest Source2 1 10 0110 00 I – – – – – – – Source1 xnor Dest Source2 1 10 0110 01 I – – – – – – – Source1 or.tf Dest Source2 1 10 0110 11 I – – – – – – – Source1 or.ft Dest Source2 1 10 0111 01 I – – – – – – – Source1 or.ff Dest Source2 1 10 0111 10 I – – – – – – – Source1 ld Dest Base 1 1 0 1 0 0 M SZ I S D – – – – – Offset ld.u Dest Base 1 10 101 M SZ I S D – – – – – Offset st Source Base 1 10 110 M SZ I S D – – – – – Offset dcache – – – – F Source2 1 1 0 1 1 1 M 0 0 I 0 0 – – – – – Source1 bsr Link – – – – – 1 1 1 0 0 0 0 0 A I – – – – – – – Offset jsr Link Base 1 11 0001 0 A I – – – – – – – Offset bbz BITNUM Source 1 1 1 0 0 1 0 0 A I – – – – – – – Target bbo BITNUM Source 1 11 0010 1 A I – – – – – – – Target bcnd Cond Source 1 11 0011 0 A I – – – – – – – Target cmp Dest Source2 1 1 1 0 1 0 0 0 0 I – – – – – – – Source1 add Dest Source2 1 1 1 0 1 1 0 0 U I – – – – – – – Source1 sub Dest Source2 1 11 0110 1 U I – – – – – – – Source1 – Reserved bit (code as 0) l Long immediate D Direct external access bit M Modify, write modified address back to register E Emulation trap bit n Rotate sense for shifting F Clear present flags S Scale offset by data size i Invert endmask SZ Size (0 = byte, 1 = halfword, 2 = word, 3 = doubleword |
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