TMS320C80GF datasheet(47/171 Pages) TI

47 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PP data-unit architecture (continued)

Rotate

C, Z, S,

or E

C, Z, S,

or E

C, Z, S,

or E

C, Z, S,

or E

C-IN

Logic

C-IN

Logic

C-IN

Logic

C-IN

Logic

C-Out

C-IN

C-Out

C-IN

C-Out

C-IN

C-Out

C-IN

Expander (Replicate)

mf Register

sr(C)

Clear

Figure 38. Multiple-Byte Arithmetic Data Flow

PP multiplier

The PP’s hardware multiplier can perform one 16x16 multiply with a 32-bit result or two 8x8 multiplies with two

16-bit results in a single cycle. A 16x16 multiply can use signed or unsigned operands as shown in Figure 39.

Signed Input

Signed

× Signed Result

Unsigned Input

Unsigned

× Unsigned Result

Figure 39. 16 x 16 Multiplier Data Formats

When performing two simultaneous 8x8 split multiplies, the first input word contains unsigned byte operands

and the second input word contains signed or unsigned byte operands. These formats are shown in Figure 40

and Figure 41.

TMS320C80GF Datasheet(PDF) 47 Page - Texas Instruments

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