TMS320C80GF datasheet(44/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

communication (comm) register

The comm register contains the packet-transfer handshake bits and PP indicator bits. Figure 32 shows the

comm register format.

–

PP#

MAREV

MIREV

DEV

MAREV

MIREV

DEV Device

High-priority packet transfer

Packet-transfer suspend

Packet transfer queued

Submit packet transfer request

Major revision #

Minor revision #

00 – 320C80

10 – 320C82

PP#

pp Number (read only)

000 – pp0

010 – pp2

001 – pp1

011 – pp3

1xx – not implemented

Figure 32. comm Register

cache-tag registers

The tag0 – tag3 registers contain the tag address and sub-block present bits for each cache block. Figure 33

shows the cache tag registers.

23-Bit Tag Address

–

LRU

Present bit

Least-recently-used code

00 – mru

10 – next lru

01 – next mru

11 – lru

Sub-Block #

Figure 33. Cache Tag Registers

PP cache architecture

Each PP has its own 2K-byte instruction cache. Each cache is divided into four blocks and each block is divided

into four sub-blocks containing 16 64-bit instructions each. Cache misses cause one sub-block to be loaded

into cache. Figure 34 shows the cache architecture for one of the four sets in each cache. Figure 35 shows how

addresses map into the cache using the cache tags and address bits.

Block 0

Block 1

Block 2

Block 3

tag 0 (Block 0)

tag 1 (Block 1)

tag 2 (Block 2)

tag 3 (Block 3)

LRU

NLRU

NMRU

MRU

LRU Stack

Figure 34. PP Cache Architecture

23-Bit Tag Value

sub

instruction

ignored

sub – sub-block

Figure 35. pc Register Cache-Address Mapping

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