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TMS320C80GF Datasheet(PDF) 68 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 68 Page - Texas Instruments |
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68 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 65 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 frame-timer control (FTCTLx) register The FTCTLx register contains mode bits to determine frame-timer behavior. 15 14 13 12 11 10 98 76 5 4321 0 FTE IFD IIM SSE FLE CPM VPM HPM FTE IFD IIM SSE FLE CPM Frame-timer enable Interlaced frame disable Interlace interrupt mode Set synchronization enable Frame lock enable CSYNC / HBLNK pin mode 00 – CSYNC Hi-Z 10 – CSYNC output 01 – CSYNC input 11 – HBLNK output VPM HPM VSYNC Pin Mode 00 – Hi-Z 10 – Output 01 – Input 11 – Reserved HSYNC Pin Mode 00 – Hi-Z 10 – Output 01 – Input 11 – Reserved Figure 49. FTCTLx Register SRT controller registers The SRT controller has two sets of 32-bit registers, one for each of the supported frame memory regions. The location of these registers in on-chip memory-mapped register space is shown in Figure 50. Address Address FMEMCTL0 0x01820300 FMEMCTL1 0x01820340 F1STADR0 0x01820304 F1STADR1 0x01820344 F0STADR0 0x01820308 F0STADR1 0x01820348 LINEINC0 0x0182030C LINEINC1 0x0182034C SAMMASK0 0x01820310 SAMMASK1 0x01820350 NEXTADR0 0x01820314 NEXTADR1 0x01820354 CRNTADR0 0x0182033C CRNTADR1 0x0182037C Figure 50. SRT Controller Register Map SRT controller register programming The register format for the frame memory control registers is shown in Figure 51. All other registers are 32-bit values. For programming details, see the TMS320C80 Video Controller User’s Guide (literature number SPRU111). FMEMCTLx Register The frame memory control (FMEMCTLx) register contains mode bits to determine operation of the associated frame memory. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H S S I L R P T S TMS EMS U E D FTS HSS ILR PTS TMS Half-SAM select Interlaced line repeat Packet transfer select Transfer mode select 00 – Display 10 – Capture 01 – Reserved 11 – Merge capture EMS UED FTS Event mode select 00 – sof, line, sam 10 – sof, line 01 – sof, eof, sam 11 – none Unblanked event disable Frame timer sequencer 00 – ft0 / disabled 10 – ft1 / disabled 01 – ft0 / enabled 11 – ft1 / enabled Figure 51. FMEMCTLx Register |
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