TMS320C80GF datasheet(29/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

MP cache architecture

The MP contains two four-way set-associative, 4K caches for instructions and data. Each cache is divided into

four sets with four blocks in each set. Each block represents 256 bytes of contiguous instructions or data and

is aligned to a 256-byte address boundary. Each block is partitioned into four sub-blocks that each contain

sixteen 32-bit words and are aligned to 64-byte boundaries within the block. Cache misses cause one sub-block

to be loaded into cache. Figure 18 shows the cache architecture for one of the four sets in each cache. Figure 19

shows how addresses map into the cache using the cache tags and address bits.

Set 0

Block 0

Block 1

Block 2

Block 3

Tag Reg 0 (Block 0)

Tag Reg 1 (Block 1)

Tag Reg 2 (Block 2)

Tag Reg 3 (Block 3)

LRU in SET 0

NLRU in SET 0

NMRU in SET 0

MRU in SET 0

LRU Stack for SET 0

Figure 18. MP Cache Architecture (x4 Sets)

32-Bit Logical Address

Set 0

Bank 0

Set 2

Bank 1

Set 1

Set 3

SS A A s

11 10 9876

WWWW B B

543210

Address in On-Chip

Cache Bank

On-Chip MP 2K Cache RAMS

T – Tag Address Bits

s – Sub-Block (within block) Select (0 – 3)

B – Byte (within word) Select (0 – 3)

S – Set Select Bits (0 – 3)

W – Word (within sub-block) Select (0 – 15)

A – Block Select (which tag matched) (0 – 3)

Figure 19. MP Cache Addressing

TMS320C80GF Datasheet(PDF) 29 Page - Texas Instruments

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