TMS320C80GF datasheet(17/171 Pages) TI

17 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

DESCRIPTION

NAME

TYPE†

DESCRIPTION

VIDEO INTERFACE

CAREA0, CAREA1

Composite area. CAREA0 and CAREA1 define a special area such as an overscan boundary. This area

represents the logical OR of the internal horizontal and vertical area signals.

CBLNK0 / VBLNK0,

CBLNK1 / VBLNK1

Composite blanking / vertical blanking. Each of CBLNK0 / VBLNK0 and VBLNK1 provides one of two

blanking functions, depending on the configuration of the CSYNC / HBLNK pin:

Composite blanking disables pixel display /capture during both horizontal and vertical retrace periods

and is enabled when CSYNC is selected for composite sync video systems.

Vertical blanking disables pixel display /capture during vertical retrace periods and is enabled when

HBLNK is selected for separate-sync video systems.

Following reset, CBLNK0 / VBLNK0 and CBLNK1 / VBLNK1 are configured as CBLNK0 and CBLNK1,

respectively.

CSYNC0 / HBLNK0,

CSYNC1 / HBLNK1

I/O/Z

Composite sync / horizontal blanking. CSYNC0 / HBLNK0 and CSYNC1 / HBLNK1 can be programmed

for one of two functions:

Composite sync is for use on composite-sync video systems and can be programmed as an input,

output, or high-impedance signal

. As an input, the ’C80 extracts horizontal and vertical sync

information from externally generated active-low sync pulses. As an output, the active-low composite

sync pulses are generated from either external HSYNC and VSYNC signals or the ’C80’s internal

video timers. In the high-impedance state, the pin is neither driven nor allowed to drive circuitry.

Horizontal blank disables pixel display / capture during horizontal retrace periods in separate-sync

video systems and can be used as an output only.

Immediately following reset, CSYNC0 / HBLNK0 and CSYNC1 / HBLNK1 are configured as

high-impedance CSYNC0 and CSYNC1, respectively.

FCLK0, FCLK1

Frame clock. FCLK0 and FCLK1 are derived from the external video system’s dotclock and are used to

drive the ’C80 video logic for frame timer 0 and frame timer 1.

HSYNC0,

HSYNC1

I/O/Z

Horizontal sync. HSYNC0 and HSYNC1 control the video system. They can be programmed as input,

output, or high impedance signals. As an input, HSYNC synchronizes the video timer to externally

generated horizontal sync pulses. As an output, HSYNC is an active-low horizontal sync pulse generated

by the ’C80 on-chip frame timer. In the high-impedance state, the pin is not driven, and no internal

synchronization is allowed to occur. Immediately following reset, HSYNC0 and HSYNC1 are in the

high-impedance state.

SCLK0, SCLK1

Serial-data clock. SCLK0 and SCLK1 are used by the ’C80 SRT controller to track the VRAM tap point

when using midline reload. SCLK0 and SCLK1 should be the same signals that clock the serial register

on the VRAMs controlled by frame timer 0 and frame timer 1, respectively.

VSYNC0,

VSYNC1

I/O/Z

Vertical sync. VSYNC0 and VSYNC1 control the video system. They can be programmed as inputs,

outputs, or high-impedance signals. As inputs, VSYNCx synchronizes the frame timer to externally

generated vertical-sync pulses. As outputs, VSYNCx are active-low vertical-sync pulses generated by the

’C80 on-chip frame timer. In the high-impedance state, the pin is not driven and no internal synchronization

is allowed to occur. Immediately following reset, VSYNCx is in the high-impedance state.

POWER

VSS‡

Ground. Electrical ground inputs

VDD‡

Power. Nominal 3.3-V power supply inputs

MISCELLANEOUS

No Connect

No connect serves as an alignment key and must be left unconnected.

FF2 – FF1

FF2 – FF1 (GF package only) are reserved for factory use and should be left unconnected.

† I = input, O = output, Z = high-impedance

‡ For proper operation, all VDD and VSS pins must be connected externally.

TMS320C80GF Datasheet(PDF) 17 Page - Texas Instruments

TMS320C80GF Datasheet(HTML) 17 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL