TMS320C80GF datasheet(91/171 Pages) TI

91 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

load-color-register cycles

Load-color-register (LCR) cycles are used to load a VRAM’s color register prior to performing a block write. LCR

cycles are supported only on 64-bit data buses. An LCR cycle closely resembles a normal write cycle because

it writes into a VRAM. The difference is that the DSF output is high at both the fall of RAS and the fall of

CAS / DQM. Also, because the VRAM color register is a single location, only one column access occurs.

The row address that is output by the TC is used for bank decode only. Normally all VRAM banks should be

selected during an LCR cycle because another LCR cycle will not occur when a block-write memory page

change occurs. The column address that is output during an LCR is likewise irrelevant because the VRAM color

The RETRY input is sampled during LCR column states and must be valid high or low. Asserting RETRY at

column time has no effect, however, because only one column access is performed.

If the BS[1:0] inputs indicate that the addressed memory supports only simulated block writes, the LCR cycle

will be changed into a normal write cycle at the start of the simulated block write. Load color register cycles timing

is shown in Figure 72 through Figure 75.

TMS320C80GF Datasheet(PDF) 91 Page - Texas Instruments