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TMS320C80GF Datasheet(PDF) 88 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 88 Page - Texas Instruments |
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88 / 171 page ![]() TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 85 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 write cycles (continued) c1 c1 c1 C C C CAS / DQM[7:0] RAS UTIME DDIN DBEN D[63:0] W TRG / CAS DSF CAS / DQM[7:0] RAS A[31:0] RL STATUS[5:0] RETRY READY FAULT UTIME PS[3:0] BS[1:0] AS[2:0] CT[2:0] CLKOUT State AB For user-modified timing: B A B A Col C Col B Col A Row PAC PAC Cycle Type r1 r2 r3 r6 rspin rspin col col ci† col r1 Col A Col B Col C 5 0 For Normal Write, 1 For PDPT Write † Internally generated pipeline bubble (example) Idle PAC Figure 69. Nonpipelined 1 Cycle / Column Write-Cycle Timing |
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