TMS320C80GF datasheet(16/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

DESCRIPTION

NAME

TYPE†

DESCRIPTION

HOST INTERFACE

HACK

Host acknowledge. The ’C80 drives HACK output low following an active HREQ to indicate that it has driven

the local-memory-bus signals to the high-impedance state and is relinquishing the bus. HACK is driven high

asynchronously following HREQ being detected inactive, and then the ’C80 resumes driving the bus.

HREQ

Host request. An external device drives HREQ low to request ownership of the local-memory bus. When

HREQ is high, the ’C80 owns and drives the bus. HREQ is synchronized internally to the ’C80’s internal clock.

Also, HREQ is used at reset to determine the power-up state of the MP. If HREQ is low at the rising edge

of RESET, the MP comes up running. If HREQ is high, the MP remains halted until the first interrupt

occurrence on EINT3.

REQ1, REQ0

Internal cycle request. REQ1 and REQ0 provide a two-bit code indicating the highest-priority memory-cycle

request that is being received by the TC. External logic can monitor REQ1 and REQ0 to determine if it is

necessary to relinquish the local-memory bus to the ’C80.

SYSTEM CONTROL

CLKIN

Input clock. CLKIN generates the internal ’C80 clocks to which all processor functions (except the frame

timers) are synchronous.

CLKOUT

Local output clock. CLKOUT provides a way to synchronize external circuitry to internal timings. All ’C80

output signals (except the VC signals) are synchronous to this clock.

EINT1, EINT2, EINT3

Edge-triggered interrupts. EINT1, EINT2 and EINT3 allow external devices to interrupt the master processor

(MP) on one of three interrupt levels (EINT1 is the highest priority). The interrupts are rising-edge triggered.

EINT3 also serves as an unhalt signal. If the MP is powered-up halted, the first rising edge on EINT3 causes

the MP to unhalt and fetch its reset vector (the EINT3 interrupt-pending bit is not set in this case).

LINT4

Level-triggered interrupt. LINT4 provides an active-low level-triggered interrupt to the MP. Its priority falls

below that of the edge-triggered interrupts. Any interrupt request should remain low until it is recognized by

the ’C80.

RESET

Reset. RESET is driven low to reset the ’C80 (all processors). During reset, all internal registers are set to

their initial state and all outputs are driven to their inactive or high-impedance levels. During the rising edge

of RESET, the MP reset mode and the ’C80’s operating endian mode are determined by the levels of HREQ

and UTIME pins, respectively.

XPT2 – XPT0

External packet transfer. XPT2 – XPT0 are used by external devices to request a high-priority XPT by the TC.

EMULATION CONTROL

EMU0, EMU1‡

I/O

Emulation pins. EMU0 and EMU1 are used to support emulation host interrupts, special functions targeted

at a single processor, and multiprocessor halt-event communications.

TCK‡

Test clock. TCK provides the clock for the ’C80 IEEE-1149.1 logic, allowing it to be compatible with other

IEEE-1149.1 devices, controllers, and test equipment designed for different clock rates.

TDI‡

Test data input. TDI provides input data for all IEEE-1149.1 instructions and data scans of the ’C80.

TDO

Test data output. TDO provides output data for all IEEE-1149.1 instructions and data scans of the ’C80.

TMS‡

Test-mode select. TMS controls the IEEE-1149.1 state machine.

TRST§

Test reset. TRST resets the ’C80 IEEE-1149.1 module. When low, all boundary-scan logic is disabled,

allowing normal ’C80 operation.

† I = input, O = output, Z = high impedance

‡ This pin has an internal pullup and can be left unconnnected during normal operation.

§ This pin has an internal pulldown and can be left unconnnected during normal operation.

TMS320C80GF Datasheet(PDF) 16 Page - Texas Instruments

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