TMS320C80GF datasheet(74/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

LOCAL MEMORY INTERFACE

status codes

Status codes are output on STATUS[5:0] to describe the cycle being performed. During row time, the

STATUS[5:0] pins indicate the type of cycle being performed. The cycle type can be latched using RL or RAS

and used by external logic to perform memory bank decoding or to enable special hardware features. During

column time, the STATUS[5:0] pins indicate the requesting processor or special column information. See

Table 29 for a listing of the Row-time status codes and Table 30 for a listing of column-time status codes.

Table 29. Row-Time Status Codes

STATUS[5:0]

CYCLE TYPE

STATUS[5:0]

CYCLE TYPE

0 0 0 0 0

Normal Read

1 0 0 0 0

Reserved

0 0 0 0 0

Normal Write

1 0 0 0 0

Reserved

0 0 0 0 1

Refresh

1 0 0 0 1

Reserved

0 0 0 0 1

SDRAM DCAB

1 0 0 0 1

Reserved

0 0 0 1 0

Peripheral Device PT Read

1 0 0 1 0

XPT1 Read

0 0 0 1 0

Peripheral Device PT Write

1 0 0 1 0

XPT1 Write

0 0 0 1 1

Reserved

1 0 0 1 1

XPT1 PDPT Read

0 0 0 1 1

Reserved

1 0 0 1 1

XPT1 PDPT Write

0 0 1 0 0

Reserved

1 0 1 0 0

XPT2 Read

0 0 1 0 0

Block Write PT

1 0 1 0 0

XPT2 Write

0 0 1 0 1

Reserved

1 0 1 0 1

XPT2 PDPT Read

0 0 1 0 1

Reserved

1 0 1 0 1

XPT2 PDPT Write

0 0 1 1 0

SDRAM MRS

1 0 1 1 0

XPT3 Read

0 0 1 1 0

Load Color Register

1 0 1 1 0

XPT3 Write

0 0 1 1 1

Reserved

1 0 1 1 1

XPT3 PDPT Read

0 0 1 1 1

Reserved

1 0 1 1 1

XPT3 PDPT Write

0 1 0 0 0

Frame 0 Read Transfer

1 1 0 0 0

XPT4 / SAM1 Read

0 1 0 0 0

Frame 0 Write Transfer

1 1 0 0 0

XPT4 / SAM1 Write

0 1 0 0 1

Frame 0 Split Read Transfer

1 1 0 0 1

XPT4 / SAM1 PDPT Read

0 1 0 0 1

Frame 0 Split Write Transfer

1 1 0 0 1

XPT4 / SAM1 PDPT Write

0 1 0 1 0

Frame 1 Read Transfer

1 1 0 1 0

XPT5 / SOF1 Read

0 1 0 1 0

Frame 1 Write Transfer

1 1 0 1 0

XPT5 / SOF1 Write

0 1 0 1 1

Frame 1 Split Read Transfer

1 1 0 1 1

XPT5 / SOF1 PDPT Read

0 1 0 1 1

Frame 1 Split Write Transfer

1 1 0 1 1

XPT5 / SOF1 PDPT Write

0 1 1 0 0

Reserved

1 1 1 0 0

XPT6 / SAM0 Read

0 1 1 0 0

Reserved

1 1 1 0 0

XPT6 / SAM0 Write

0 1 1 0 1

Reserved

1 1 1 0 1

XPT6 / SAM0 PDPT Read

0 1 1 0 1

Reserved

1 1 1 0 1

XPT6 / SAM0 PDPT Write

0 1 1 1 0

PT Read Transfer

1 1 1 1 0

XPT7 / SOF0 Read

0 1 1 1 0

PT Write Transfer

1 1 1 1 0

XPT7 / SOF0 Write

0 1 1 1 1

Reserved

1 1 1 1 1

XPT7 / SOF0 PDPT Read

0 1 1 1 1

Idle

1 1 1 1 1

XPT7 / SOF0 PDPT Write

TMS320C80GF Datasheet(PDF) 74 Page - Texas Instruments

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