TMS320C80GF datasheet(77/171 Pages) TI

77 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

cycle time selection

The ’C80 supports eight basic sets of memory timings to support various memory types directly. The cycle timing

is selected by the value input on the CT[2:0] and UTIME pins at row time. The selected timing remains in effect

until the next row access. See Table 32 for Cycle-timing selections.

Table 32. Cycle-Timing Selection

UTIME

CT[2:0]

MEMORY TIMING

Reserved

SDRAM: burst length 1, read latency 4

Reserved

SDRAM: burst length 2, read latency 4

User timed DRAM: pipelined 1 cycle / column

User timed DRAM: 1 cycle / column

User timed DRAM: 2 cycle / column

User timed DRAM: 3 cycle / column

SDRAM: burst length 1, read latency 2

SDRAM: burst length 1, read latency 3

SDRAM: burst length 2, read latency 2

SDRAM: burst length 2, read latency 3

DRAM: pipelined 1 cycle / column

DRAM: 1 cycle / column

DRAM: 2 cycle / column

DRAM: 3 cycle / column

page sizing

Whenever an external memory access occurs, the TC records the 26 most significant bits of the address in its

internal LASTPAGE register. The address of each subsequent (column) access is compared to this value. The

page size value input on the PS[3:0] pins determines which bits of LASTPAGE are used for this comparison.

If a difference exists between the enabled LASTPAGE bits and the corresponding bits of the next access then

the page has changed and the next memory access begins with a new row-address cycle (see Table 33).

TMS320C80GF Datasheet(PDF) 77 Page - Texas Instruments