TMS320C80GF datasheet(101/171 Pages) TI

101 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

transfer cycles

Read-transfer (memory-to-register) cycles transfer a row from the VRAM memory array into the VRAM shift

Split-register read-transfer (memory-to-split-register) cycles also transfer data from a row in the memory array

to the SAM. However, these transfers cause only half of the SAM to be written. Split-register read transfers allow

the inactive half of the SAM to be loaded with the new data while the other active half continues to shift data

in or out.

Write-transfer (register-to-memory) cycles transfer data from the SAM into a row of the VRAM array. This

transfer causes the entire SAM (both halves of the split SAM) to be written into the array.

Split-register write-transfer (split-register-to-memory) cycles also transfer data from the SAM to a row in the

memory array. However, these transfers write only half of the SAM into the array. Split-register write transfers

allow the inactive half of the SAM to be transferred into memory while the other (active) half continues to shift

serial data in or out.

Read and split-read transfers resemble a standard read cycle. Write and split-write transfers resemble a

standard write cycle. The TRG / CAS output is driven low prior to the fall of RAS to indicate a transfer cycle. Only

a single column access is performed so RETRY, while required to be at a valid level, has no effect if asserted

at column time. The value output on A[31:0] at column time represents the SAM tap point (see Figure 80 through

Figure 86 for transfer cycle timing.

TMS320C80GF Datasheet(PDF) 101 Page - Texas Instruments