8101 datasheet(124/172 Pages) LSI

124 / 172 page

4-36

Registers

4.3.23 Register 112–115–Counter Half Full 1

−4

Note:

HFULL[15] 15-bit occurs on the REGD15 pin.

HFULL[15:0]

Counter Half Full Detect

[15:0], R/LHI

These bits indicate when a counter is near overﬂow is

half full. These four registers contain 53 counter half-full

detect bits, one bit for each of the 53 counters.

Bit 0 in Counter Half Full Register 0 corresponds to

Counter 1 as listed in Table 4.1; bit 15 in Counter Half

Full Register 0 corresponds to Counter 16; bit 4 of

Counter Half Full Register 4 corresponds to Counter 53.

4.3.24 Registers 120–123–Counter Half Full Mask 1

−4

Note:

MASK_HFULL[15] 15-bit occurs on the REGD15 pin

MASK_HFULL[15:0]

Counter Half Full Detect Mask

[15:0], R/W

The MASK_HFULL[15:0] bits mask (disable) the interrupt

caused by the counter half-full detect bits. These four

registers contain 53 mask bits, one bit for each of the 53

half-full detect bits.

Bit 0 in Counter Half Full Mask Register 0 masks the

interrupt caused by the half full detect bit for Counter 1;

bit 15 in Counter Half Full Mask Register 0 corresponds

to Counter 16; bit 4 in Counter Half Full Mask Register 3

corresponds to Counter 53.

HFULL[15:0]

Description

Counter has reached a count of 0x80000000,

(half full).

Count

< 0x80000000

MASK_HFULL[15:0]

8101 Datasheet(PDF) 124 Page - LSI Computer Systems