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8101 Datasheet(PDF) 125 Page - LSI Computer Systems |
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8101 Datasheet(HTML) 125 Page - LSI Computer Systems |
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125 / 172 page  Register Definitions 4-37 Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved. 4.3.25 Registers 128 −233–Counter 1−53 Note: C15 15-bit occurs on the REGD15 pin. C[15:0] Counter Result Value [15:0], R These 106 registers contain the results of the 53 32-bit management counters. Each 32-bit counter result value resides in two 16-bit registers. For the two registers associated with each counter, the register with the lower value address always contains the least-significant 16 bits of the counter result. C0 of the lower value address is the counter LSB; C15 of the higher value is the counter MSB. The definition and register address for each counter is shown in Table 2.14. The register address for each counter is also shown in Table 4.2. MASK_HFULL[15:0] Description 1 Mask (disable) the interrupt caused by the corresponding Counter Half Full Detect Bit. 0 No mask 15 0 C[15:0] |
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