8101 datasheet(129/172 Pages) LSI

129 / 172 page

System Interface

5-3

5.2.2 Printed Circuit Board Layout

The 10-bit PHY interface clocks data at 125 MHz. The setup and hold

times on the timing signals are very short. The outputs are speciﬁed

assuming a maximum load of only 10 pf. For these reasons, it is

imperative that the SerDes or other physical layer device be placed as

close as possible to the controller, preferably within one inch. In addition,

care should be taken to eliminate any extra loading on all the 10-bit PHY

interface signal lines. Also, the clock and data lines in both receive and

transmit directions should be routed along the same paths so that they

have similar parasitics and delays, to prevent degrading setup and hold

times. Termination is not necessary if these precautions are taken.

5.3 System Interface

The system interface requires the selection of watermarks and close

attention to printed circuit board layout.

5.3.1 Watermarks

There are two independent watermarks on both the transmit and receive

FIFOs. The usage of these watermarks is unspeciﬁed and is left to the

discretion of the system designer. Below are three examples of

watermark usage based on transferring data in any of the following ways:

• Complete packets

• Fixed block sizes

• Variable block sizes

Table 5.1

Compatible SerDes Devices

Vendor

Device No.

Vitesse

VSC7135

Hewlett-Packard

HDMP-1636

HDMP-1646

Sony

CXB1589Q

AMCC

52052

TriQuint

TQ9506

8101 Datasheet(PDF) 129 Page - LSI Computer Systems