8101 datasheet(130/172 Pages) LSI

130 / 172 page

5-4

Application Information

5.3.1.1 Complete Packet Watermarks

To transfer data to and from the controller in completed packets, only one

watermark is needed. Either transmit watermark could be chosen for this

application. On the receive side, RXWM2 should be chosen because it

is asserted when a complete packet is loaded into the RX FIFO. The

transmit and receive watermark thresholds should preferably be set to a

value equal to or larger than the maximum size packet (1518 bytes or

greater). On the transmit side, the data is written into the TX FIFO in

complete packet bursts when the system requires. On the receive side

the data is read out of the RX FIFO beginning with the assertion of

RXWM2 and ending when RXEOF is asserted.

5.3.1.2 Fixed Block Watermarks

To transfer data to and from the controller in ﬁxed block sizes (64 bytes

at a time, for example), only one watermark is needed. Either transmit

watermark could be chosen for this application. On the receive side,

RXWM2 should be chosen because it is asserted when a complete

packet is loaded into the RX FIFO. The transmit watermark threshold is

set to a low value (64 bytes for example), and the receive watermark

thresholds preferably are set to a value equal to or greater than the ﬁxed

cell size (64 bytes in this example). On the transmit side, the data is

written into the TX FIFO in ﬁxed block size bursts when the system

requires. When the transmit watermark is deasserted, another block

must be written into the TX FIFO. On the receive side, the data is read

out of the RX FIFO beginning with the assertion of RXWM2 and ending

when the ﬁxed block has been read out (64 bytes in this example) or

RXEOF has been asserted.

5.3.1.3 Variable Block Watermarks

To transfer data to and from the controller in variable cell sizes, two

watermarks are needed. The TXWM1n and RXWM1 watermark

thresholds are set to some low value (64 bytes for this example) while

the TXWM2n and RXWM2 watermark thresholds are set to some high

value (1024 bytes for example). On the transmit side, the data is written

into the TX FIFO when the system requires. If TXWM2n is asserted, the

data input must be halted. If TXWM1n is deasserted, the data input must

be resumed. In this way, the TX FIFO contents are kept between the high

and low watermark thresholds, which potentially increses the external

8101 Datasheet(PDF) 130 Page - LSI Computer Systems