8101 datasheet(131/172 Pages) LSI

131 / 172 page

Reset

5-5

system loading efﬁciency. Similarly, on the receive side the data must be

read out of the RX FIFO when RXWM2 is asserted. If RXWM1 is

deasserted, or RXEOF is asserted, the data output must be halted. If

RXWM2 is asserted the data output must be resumed. In this way, the

RX FIFO contents are kept between the high and low watermarks.

The transmit and receive watermarks can also be used to indicate that

the FIFO is full or empty (or almost full or almost empty), if desired.

5.3.2 PCB Layout

Because the data rate of the system interface can be as high as 66 MHz,

care should be taken to keep PCB trace lengths of all critical signals as

short as possible, preferably less than 2 inches in length. If this guideline

is followed termination is not necessary.

5.4 Reset

While the device is being reset, it transmits valid 10B symbols out of the

10-bit PHY interface on TXD[0:9] and TBC. If the device is reset with the

RESETn pin for a long period of time, these 10B symbols may be

mistakenly decoded as valid packet information and ﬁll up the memory

in a remote device. The reset procedure outlined in Table 5.2 avoids this

situation and is recommended for use when the RESETn pin is asserted

for long periods of time. When the reset bit is used for device reset the

above situation is avoided because the reset bit is self-clearing in 1

µs.

8101 Datasheet(PDF) 131 Page - LSI Computer Systems