S5335 datasheet(14/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

PCI Operation Registers

The second group of registers are the PCI Operation

Registers shown in Table 2. This group consists of six-

teen 32-bit (DWORD) registers accessible to the Host

processor from the PCI Local bus. These are the main

registers through which the PCI Host configures

S5335 operation and communicates with the Add-On

Local bus. These registers encompass the PCI bus

incoming and outgoing Mailboxes, FIFO data channel,

Bus Master Address and Count registers, Pass-Thru

data channel registers and S5335 device Status and

Control registers.

Add-On Bus Operation Registers

The third and last register group consists of the Add-

On Operation Registers, shown in Table 3. This group

of eighteen 32-bit (DWORD) registers is accessible to

the Add-On Local bus. These are the main registers

through which the Add-On logic configures S5335

operation and communicates with the PCI Local bus.

These registers encompass the Add-On bus Mail-

boxes, Add-On FIFO, DMA Address/Count Registers

(when Add-On initiated Bus Mastering), Pass-Thru

Registers and Status/Control registers.

Non-Volatile Memory Interface

The S5335 contains a set of PCI Configuration Regis-

ters. These registers can be initialized with default

values or with designer specified values contained in

an external nvRAM. The nvRAM can be either a serial

(2 Kbytes, maximum) or a byte-wide device (64

Kbytes, maximum).

PCI Status

PCI Command

04h

Class Code

Revision ID

08h

Built-in

Self Test

Header

Type

Latency

Timer

Cache

Line Size

0Ch

Base Address Register 0

10h

Base Address Register 1

14h

Base Address Register 2

18h

Base Address Register 3

1Ch

Base Address Register 4

20h

Reserved

24h

Reserved Space

28h

Reserved Space

2Ch

Expansion ROM Base Address

30h

Reserved Space

34h

Reserved Space

38h

Max.

Latency

Min. Grant

Interrupt

Line

3Ch

Table 1. PCI Configuration Registers (Continued)

Byte 3

Byte 2

Byte 1

Byte 0

Address

Table 2. PCI Operation Registers

PCI Operation Registers

Address

Offset

Outgoing Mailbox Register 1 (OMB1)

00h

Outgoing Mailbox Register 2 (OMB2)

04h

Outgoing Mailbox Register 3 (OMB3)

08h

Outgoing Mailbox Register 4 (OMB4)

0Ch

Incoming Mailbox Register 1 (IMB1)

10h

Incoming Mailbox Register 2 (IMB2)

14h

Incoming Mailbox Register 3 (IMB3)

18h

Incoming Mailbox Register 4 (IMB4)

1Ch

FIFO Register Port (bidirectional) (FIFO)

20h

Master Write Address Register (MWAR)

24h

Master Write Transfer Count Register (MWTC)

28h

Master Read Address Register (MRAR)

2Ch

Master Read Transfer Count Register (MRTC)

30h

Mailbox Empty/Full Status Register (MBEF)

34h

Interrupt Control/Status Register (INTCSR)

38h

Bus Master Control/Status Register (MCSR)

3Ch

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