S5335 datasheet(25/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

SELECT#

Select for the Add-On interface. This signal must be driven low for any write or read access to the Add-

On interface registers. This signal must be stable during the assertion of command signals WR# or

RD#.

WR#

Write strobe. This pin, when asserted in conjunction with the SELECT# pin, causes the writing of one

of the internal registers. The specific register and operand size are identified through address pins

ADR[6:2] and the byte enables, BE[3:0]#.

RD#

Read strobe. This pin, when asserted in conjunction with the SELECT# pin, causes the reading of one

of the internal registers. The specific register and operand size are identified through address pins

ADR[6:2] and the byte enables BE[3:0]#.

MODE

This pin control whether the S5335 data accesses on the DQ bus are to be 32-bits wide (MODE = low)

or 16-bits wide (MODE = high). When in the 16 bit mode, the signal BE3# is reassigned as the address

signal ADR1. MODE has an internal 50k Ohm pull-up resistor.

Table 13. FIFO Access Pins

Signal

Type

Description

WRFIFO#

Write FIFO. This signal provides a method to directly write the FIFO without having to generate the

SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO. Access width is either 32 bits

or 16 bits depending on the data bus size available. This signal is intended for implementing PCI DMA

transfers with the Add-On system. WRFIFO# has an internal 50k Ohm pull-up resistor.

RDFIFO#

Read FIFO. This signal provides a method to directly read the FIFO without having to generate the

SELECT# signal or the ADR[6:2] value of [01000b] to access the FIFO. Access width is either 32 bits

or 16 bits, depending on the data bus size defined by the MODE pin. This signal is intended for imple-

menting PCI DMA transfers with the Add-On system. RDFIFO# has an internal 50k Ohm pull-up resis-

tor.

WRFULL

out

Write FIFO full. This pin indicates whether the Add-On-to-PCI bus FIFO is able to accept more data.

This pin is intended to be used to implement DMA hardware on the Add-On system bus. A logic low

output from this pin can be used to represent a DMA write (Add-On to-PCI FIFO) request.

RDEMPTY

out

Read FIFO Empty. This pin indicates whether the read FIFO (PCI-to-Add-On FIFO) contains data.

This pin is intended to be used by the Add-On system to control DMA transfers from the PCI bus to the

Add-On system bus. A logic low from this pin can be used to represent a DMA (PCI-to-Add-On FIFO)

request.

Table 14. Pass-Thru Interface Pins

Signal

Type

Description

PTATN#

out

Pass-Thru Attention. This signal identifies that an active PCI bus cycle has been decoded and data

must be read from or written to the Pass-Thru Data Register.

PTBURST#

out

Pass-Thru Burst. This signal identifies PCI bus operations involving the current Pass-Thru cycle as

requesting burst access.

PTRDY#

Pass-Thru Ready. This input indicates when Add-On logic has completed a Pass-Thru cycle and

another may be initiated.

PTNUM[1:0]

out

Pass-Thru Number. These signals identify which of the four base address registers decoded a Pass-

Thru bus activity. These bits are only meaningful when signal PTATN# is active. A value of 00 corre-

sponds to Base Address Register 1, a value of 01 for Base Address Register 2, and so on.

Table 12. Register Access Pins (Continued)

Signal

Type

Description

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