S5335 datasheet(84/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

Add-On Controlled Bus Master Read Transfer

Count Register (MRTC)

This register is only accessible when Add-On initiated

bus mastering is enabled.

The master read transfer count register is used to con-

vey to the PCI controller the actual number of bytes

that are to be transferred. The value in this register is

decremented with each bus master PCI read opera-

tion until the transfer count reaches zero. Upon

reaching zero, the transfer operation ceases and an

interrupt may be optionally generated to either the PCI

or Add-On bus interface. Transfers which are not

whole multiples of DWORDs in size result in a partial

word ending cycle. This partial word ending cycle is

possible since all bus master transfers for this control-

ler are required to begin on a DWORD boundary.

Figure 38. Add-On Controlled Bus Master Read Transfer Count Register

Master Read Transfer Count

Add-On Address Offset:

5Ch

Power-up value:

00000000h

Attribute:

Read/Write

Size:

32 bits

Bit

Value

Transfer Count

in Bytes (R/W)

Reserved = 0's (RO)

S5335 Datasheet(PDF) 84 Page - Applied Micro Circuits Corporation