S5335 datasheet(33/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

PCI Status Register (PCISTS)

This 16-bit register contains the PCI status informa-

tion. The function of this register is defined by the PCI

specification and its implementation is required of all

PCI devices. Only some of the bits are used by this

device; those which are not used are hardwired to 0.

Most status bits within this register are designated as

“write clear,” meaning that in order to clear a given bit,

the bit must be written as a 1. All bits written with a 0

are left unchanged. These bits are identified in Figure

10 as (R/WC). Those which are Read Only are shown

as (RO) in Figure 10.

Figure 10. PCI Status Register

PCI Status

Address Offset:

06h-07h

Power-up value:

0080h

Boot-load:

not used

Attribute:

Read Only (RO), Read/Write Clear

(R/WC)

Size:

16 bits

Reserved (RO)

Signaled Target Abort (R/WC)

Received Target Abort (R/WC)

Received Master Abort (R/WC)

Signaled System Error (R/WC)

Detected Parity Error (R/WC)

Reserved (RO) = 00's

Fast Back-to-Back (RO)

Data Parity Reported (R/WC)

DEVSEL# Timing Status (RO)

0 0 = Fast (S5335)

0 1 = Medium

1 0 = Slow

1 1 = Reserved

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