S5335 datasheet(95/189 Pages) AMCC

95 / 189 page

S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

Read accesses from the S5335 operation registers

(S5335 as a target) are shown in Figure 47. The

S5335 conditionally asserts STOP# in clock period 3 if

the initiator keeps FRAME# asserted during clock

period 2 with IRDY# asserted (indicating a burst is

being attempted). Wait states may be added by the ini-

tiator by not asserting the signal IRDY# during clock 3

and beyond. If FRAME# remains asserted, but IRDY#

is not asserted, the initiator is just adding wait states,

not necessarily attempting a burst.

There is only one condition where accesses to S5335

operation registers do not return TRDY# but do assert

STOP#. This is called a target-initiated termination or

target disconnect and occurs when a read attempt is

made to an empty S5335 FIFO. The assertion of

STOP# without the assertion of TRDY# indicates that

the initiator should retry the operation later.

When burst read transfers are attempted to the S5335

operation registers, STOP# is asserted during the first

data transfer to indicate to the initiator that no further

transfers (data phases) are possible. This is a target-

initiated termination where the target disconnects after

the first data transfer. Figure 48 shows the signal rela-

tionships during a burst read attempt to the S5335

operation registers.

Figure 47. Single Data Phase PCI Bus Read of S5335 Registers (S5335 as Target)

Figure 48. Burst PCI Bus Read Attempt to S5335 Registers (S5335 as Target)

FRAME #

AD[31:0]

C/BE[3:0]#

IRDY#

TRDY#

DEVSEL#

ST O P#

ADDRESS

DAT A

BYT E ENABLES

BUS

COMMAND

(I)

(T)

(I)

(T)

(I)

= DRIVEN BY INIT IAT OR

(T ) = DRIVEN BY T ARGET

PCI CLOCK

FRAME #

AD[31:0]

C/BE[3:0]#

IRDY#

TRDY#

DEVSEL#

ST O P#

ADDRESS

DATA

BYTE ENABLES (1)

(I)

)

(T)

(I)

BE(2)

BUSCOMMAND

(I) = DRIVEN BY INITIATOR

(T) = DRIVEN BY TARGET

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