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S5335 Datasheet(PDF) 70 Page - Applied Micro Circuits Corporation |
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S5335 Datasheet(HTML) 70 Page - Applied Micro Circuits Corporation |
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70 / 189 page  S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 70 Data Sheet ADD-ON BUS OPERATION REGISTERS The Add-On bus interface provides access to 18 DWORDs (72 bytes) of data, control and status infor- mation. All of these locations are accessed by asserting the Add-On bus chip select pin (SELECT#) in conjunction with either the read or write control strobes (signal pin RD# or WR#). Access to the FIFO can also be achieved through use of the dedicated pins, RDFIFO# and WRFIFO#. The dedicated pins for control of the FIFO are provided to optionally imple- ment Direct Memory Access (DMA) on the Add-On bus, or to connect with an external FIFO. This register group represents the primary method for communication between the Add-On and PCI buses as viewed by the Add-On. The flexibility of this arrangement allows a number of user-defined soft- ware protocols to be built. For example, data, software assigned commands, and command parameters can be exchanged between the PCI and Add-On buses using either the mailboxes or FIFOs with or without handshaking interrupts. The register structure is very similar to that of the PCI operation register set. The major difference between the PCI bus and Add-On bus register complement are the absence of bus mas- ter control registers (4) on the Add-On side and the addition of two “pass-through” registers. Table 47 lists the Add-On interface registers. 1. See Add-On Initiated Bus Mastering. Table 47. Operation Registers — Add-On Interface Address Abbreviation Register Name 00h AIMB1 Add-On Incoming Mailbox Register #1 04h AIMB2 Add-On Incoming Mailbox Register #2 08h AIMB3 Add-On Incoming Mailbox Register #3 0Ch AIMB4 Add-On Incoming Mailbox Register #4 10h AOMB1 Add-On Outgoing Mailbox Register #1 14h AOMB2 Add-On Outgoing Mailbox Register #2 18h AOMB3 Add-On Outgoing Mailbox Register #3 1Ch AOMB4 Add-On Outgoing Mailbox Register #4 20h AFIFO Add-On FIFO port 24h MWAR1 Bus Master Write Address Register 28h APTA Add-On Pass-Through Address 2Ch APTD Add-On Pass-Through Data 30h MRAR1 Bus Master Read Address Register 34h AMBEF Add-On Mailbox Empty/Full Status 38h AINT Add-On Interrupt control 3Ch AGCSTS Add-On General Control and Status Register 58h MWTC1 Bus Master Write Transfer Count 5Ch MRTC1 Bus Master Read Transfer Count |
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