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S5335 Datasheet(PDF) 24 Page - Applied Micro Circuits Corporation |
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S5335 Datasheet(HTML) 24 Page - Applied Micro Circuits Corporation |
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24 / 189 page  S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 24 Data Sheet ADD-ON BUS INTERFACE SIGNALS The following sets of signals represent the interface pins available for the Add-On function. There are four groups: Register access, FIFO access, Pass-Thru mode pins, and general system pins. Table 12. Register Access Pins Signal Type Description DQ[31:00] t/s Datapath DQ0–DQ31. These pins represent the datapath for the Add-On peripheral’s data bus. They provide the interface to the controller’s FIFO and other registers. When MODE = VCC, only DQ[15:00] are used. DQ[31:0] have internal 50k Ohm pull-up resistors. ADR[6:2] in Add-On Addresses. These signals are the address lines to select which of the 16 DWORD registers within the controller is desired for a given read or write cycle, as shown in the table below. ADR[6:2] Register Name 0 0 0 0 0 Add-On Incoming Mailbox Reg. 1 0 0 0 0 1 Add-On Incoming Mailbox Reg. 2 0 0 0 1 0 Add-On Incoming Mailbox Reg. 3 0 0 0 1 1 Add-On Incoming Mailbox Reg. 4 0 0 1 0 0 Add-On Outgoing Mailbox Reg. 1 0 0 1 0 1 Add-On Outgoing Mailbox Reg. 2 0 0 1 1 0 Add-On Outgoing Mailbox Reg. 3 0 0 1 1 1 Add-On Outgoing Mailbox Reg. 4 0 1 0 0 0 Add-On FIFO Port 0 1 0 0 1 Bus Master Write Address Register 0 1 0 1 0 Add-On Pass-Thru Address 0 1 0 1 1 Add-On Pass-Thru Data 0 1 1 0 0 Bus Master Read Address Register 0 1 1 0 1 Add-On Mailbox Empty/Full Status 0 1 1 1 0 Add-On Interrupt Control 0 1 1 1 1 Add-On General Control/Status Register 1 0 1 1 0 Bus Master Write Transfer Count 1 0 1 1 1 Bus Master Read Transfer Count BE3# or ADR1 in Byte Enable 3 (32-bit mode) or ADR1 (16 bit mode). This pin is used in conjunction with the read or write strobes (RD# or WR#) and the Add-On select signal, SELECT#. As a Byte Enable, it is neces- sary to have this pin asserted to perform write operations to the register identified by ADR[6:2] bit loca- tions d24 through d31; for read operations it controls the DQ[31:24] output drive. BE3# has an internal 50k Ohm pull-up resistor. BE[2:0]# in Byte Enable 2 through 0. These pins provide for individual byte control during register read or write operations. BE2# controls activity over DQ[23:DQ16], BE1# controls DQ[15:8], and BE0# controls DQ[7:0]. During read operations they control the output drive for each of their respective byte lanes; for write operations they serve as a required enable to perform the modification of each byte lane. BE[2:0]# have internal 50k Ohm pull-up resistors. |
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