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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

Table 5. System Pins — PCI Local Bus

Signal

Type

Description

CLK

Clock. The rising edge of this signal is the reference upon which all other signals are based, with the

exception of RST# and the interrupt (IRQA#-). The maximum frequency for this signal is 33 MHz and the

minimum is DC (0 Hz).

RST#

Reset. This signal is used to bring all other signals within this device to a known, consistent state. All PCI

bus interface output signals are not driven (tri-stated), and open drain signals such as SERR# are floated.

Table 6. Interface Control Pins — PCI Bus Signal

Signal

Type

Description

FRAME#

s/t/s

Frame. This signal is driven by the current bus master and identifies both the beginning and duration of

a bus operation. When FRAME# is first asserted, it indicates that a bus transaction is beginning and

that valid addresses and a corresponding bus command are present on the AD[31:00] and C/BE[3:0]

lines. FRAME# remains asserted during the data transfer portion of a bus operation and is deasserted

to signify the final data phase.

IRDY#

s/t/s

Initiator Ready. This signal is sourced by the bus master and indicates that the bus master is able to

complete the current data phase of a bus transaction. For write operations, it indicates that valid data is

on the AD[31:00] pins. Wait states occur until both TRDY# and IRDY# are asserted together.

TRDY#

s/t/s

Target Ready. This signal is sourced by the selected target and indicates that the target is able to com-

plete the current data phase of a bus transaction. For read operations, it indicates that the target is pro-

viding valid data on the AD[31:00] pins. Wait states occur until both TRDY# and IRDY# are asserted

together.

STOP#

s/t/s

Stop. The Stop signal is sourced by the selected target and conveys a request to the bus master to stop

the current transaction.

LOCK#

Lock. The lock signal provides for the exclusive use of a resource. The S5335 may be locked as a tar-

get by one master at a time. The S5335 cannot lock a target when it is a master.

IDSEL

Initialization Device Select. This pin is used as a chip select during configuration read or write opera-

tions.

DEVSEL#

s/t/s

Device Select. This signal is sourced by an active target upon decoding that its address and bus com-

mands are valid. For bus masters, it indicates whether any device has decoded the current bus cycle.

Table 7. Arbitration Pins (Bus Masters Only) — PCI Local Bus

Signal

Type

Description

REQ#

out

Request. This signal is sourced by an agent wishing to become the bus master. It is a point-to-point signal

and each master has its own REQ#.

GNT#

Grant. The GNT# signal is a dedicated, point-to-point signal provided to each potential bus master and sig-

nifies that access to the bus has been granted.

S5335 Datasheet(PDF) 21 Page - Applied Micro Circuits Corporation

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