S5335 datasheet(74/189 Pages) AMCC

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S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

Add-On Controlled Bus Master Read Address

This register is only accessible when Add-On initiated

bus mastering is enabled.

This register is used to establish the PCI address for

data moving to the Add-On bus from the PCI bus dur-

ing PCI bus memory read operations. It consists of a

30-bit counter with the low-order two bits hardwired as

zeros. Transfers may be any non-zero byte length as

defined by the transfer count register, MRTC and must

begin on a DWORD boundary. This DWORD bound-

ary starting constraint is placed upon this controller’s

PCI bus master transfers so that byte lane alignment

can be maintained between the S5335 controller’s

internal FIFO data path, the Add-On interface and the

PCI bus.

Note: Applications which require a non-DWORD start-

ing boundary will need to move the first few bytes

under software program control (and without using the

FIFO) to establish a DWORD boundary. After the

DWORD boundary is established the S5335 can begin

the task of PCI bus master data transfers.

The Master Read Address Register is continually

updated during the transfer process and will always be

pointing to the next unread location. Reading of this

S5335 controller is functioning as a target—i.e., not a

bus master) is permitted and may be used to monitor

the progress of the transfer. During the address phase

for bus master read transfers, the two least significant

bits presented on the PCI bus AD[31:0] will always be

zero. This identifies to the target memory that the burst

address sequence will be in a linear order rather than

in an Intel 486 or Pentium™ cache line fill sequence.

Also, the PCI bus address bit A1 will always be zero

when this controller is the bus master. This signifies to

the target that the controller is burst capable and that

the target should not arbitrarily disconnect after the

first data phase of this operation.

Under certain circumstances, MRAR can be accessed

from the Add-On bus instead of the PCI bus.

Figure 33. Add-On Controlled Bus Master Read Address Register

Master Read Address

Add-On Address Offset:

30h

Power-up value:

00000000h

Attribute:

Read/Write

Size:

32 bits

2Bit

Value

DWORD Address (RO)

Read Transfer Address (R/W)

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