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S5335 Datasheet(PDF) 40 Page - Applied Micro Circuits Corporation |
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S5335 Datasheet(HTML) 40 Page - Applied Micro Circuits Corporation |
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40 / 189 page  S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 40 Data Sheet Cache Line Size Register (CALN) This register is hardwired to 0. The cache line configu- ration register is used by the system to define the cache line size in double-word (64-bit) increments. This controller does not use the “Memory Write and Invalidate” PCI bus cycle commands when operating in the bus master mode, and therefore does not inter- nally require this register. When operating in the target mode, this controller does not have the connections necessary to “snoop” the PCI bus and accordingly cannot employ this register in the detection of burst transfers that cross a line boundary. Figure 13. Cache Line Size Register Register Name: Cache Line Size Address Offset: 0Ch Power-up value: 00h, hardwired Boot-load: not used Attribute: Read Only Size: 8 bits 7 0 00h Cache Line Size (RO) |
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